1. Field of the Invention
The invention relates to a signal generating technique, more particularly to a power-on reset circuit for generating a reset signal.
2. Description of the Related Art
In general, conventional signal processing systems are initialized by a reset signal so as to ensure operation starting of the conventional signal processing systems from a predetermined status.
In most cases, the conventional power-on reset circuit 7 shown in FIG. 1 is an analog circuit, and includes a resistor 71, a capacitor 72, and a comparator 73. When a voltage across the capacitor 72, as charged by a supply voltage (VDD), is greater than a reference voltage, a reset signal generated by the comparator 73 changes from a first predetermined logic level (0) to a second predetermined logic level (1) such that a signal processing system 6 is driven to enter an operating mode from an initial mode. On the other hand, when the capacitor 72 is discharged as a result of removal of the supply voltage (VDD) such that the voltage across the capacitor 72 is lower than the reference voltage, the reset signal changes from the second predetermined logic level (1) to the first predetermined logic level (0).
However, since the charging/discharging rate of the capacitor 72 depends on the manufacturing process thereof, it is difficult to control transition timing of the reset signal of various power-on reset circuits, even though their circuits are of the same type.
Referring to FIG. 2, U.S. Pat. No. 6,970,026 discloses another conventional analog power-on reset circuit 8. The power-on reset circuit 8 includes an oscillator 81, a frequency detector 82 including two capacitors (C1, C2), and a comparator 83. The oscillator 81 generates an oscillating signal (ck). The capacitors (C1, C2) are charged/discharged by a supply voltage (VDD) at a rate that depends on a switching frequency of the oscillating signal (ck). Therefore, as compared to the conventional power-on reset circuit 7 of FIG. 1, the transition point of the reset signal generated by the comparator 83 between the first and second predetermined logic levels (0, 1) can be more precisely determined.
However, a large supply voltage (VDD) is required for operation of the conventional power-on reset circuits 7, 8. Since the signal processing system 6 may be a digital circuit, or a circuit that requires less operating power, when the signal processing system 6 and the conventional power-on reset circuit 8 are coupled to the same supply voltage, during gradual increase of the supply voltage from zero to a steady voltage level (i.e., VDD), the signal processing system 6 may enter the operating mode prior to transition of the reset signal from the first predetermined logic level (0) to the second predetermined logic level (1). As a result, the signal processing system 6 may not have entered the operating mode from the initial mode, which is desirable, and may thus create unexpected consequences and problems.